Synthesis of Sequential Circuits with Dynamic Power Management

With increasing sizes of designs and the need for low power applications, power is another optimization constraint that has become critical in addition to timing and area for electronic circuits. The work presented in this paper exploits a fundamental and important source of power reduction – shutting down useless parts of a sequential circuit. This idea is known as power management. In our approach, the problem of low power synthesis corresponds to an optimal decomposition of a finite state machine that is a mathematical model of a sequential circuit. The proposed techniques leads to a general low power synthesis methodology based on functional partitioning of digital systems.